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A VHDL Implementation of Ternary Arithmetic and Logic Unit for Multi Valued Processor
Satish S. Narkhede, , Gajanan K. Kharate
Published in CiiT
Volume: 7.0
Issue: 6.0
Pages: 185.0 - 193.0
Multi valued processors are promising choices for future computing technology. Multi Valued Logic [MVL] has seen major advancement in the recent past due to several advantages offered by them over the binary logic, thus making it a thrust area for further research. The switching algebra has expanded from binary to penta level, progressing through ternary and quaternary levels. The processors designed with multi valued logic will revolutionize the digital world. Arithmetic Logic Unit [ALU] forms an inherent entity of every processor. This paper presents a novel and an efficient technology dependent method for defining, analyzing, testing and implementing vectored ternary ALU using Very-High-Speed Integrated Circuits, VHSIC Hardware Description Language [VHDL]. The implementation of sub-program overloading feature in the proposed Ternary ALU [TALU] makes its design unique, flexible and portable for further extension. The designed 4 – trit TALU performs a variety of arithmetic and logical operations. The timing performance of the proposed TALU signifies encouraging results that will pave the path for further developments in ternary processors.
About the journal
JournalInternational Journal of Programmable Device Circuits and Systems
Open Access0