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Design and comparison of multiplier using vedic mathematics
Published in Institute of Electrical and Electronics Engineers Inc.
2016
Volume: 2
   
Abstract
Digital signal processors (DSPS) fundamentally contains multipliers as its core element. The speed of the multipliers affects the speed of the DSPs. The execution of most DSPs is dependent on its multipliers, and hence need for high-speed multipliers arises. In this digitalization era, it becomes necessary to increase the speed of the digital circuits while reducing on-chip area and memory consumption. Latency and throughput are the basic parameters associated with multiplication algorithms where latency is a total delay in computing a function while throughput is the measure of computations performed in a given stipulated time. For increasing multiplication speed and reducing delay there is more and more emphasis on designing faster multipliers. There are many algorithms like standard modified booth algorithm, Wallace tree methods and several new techniques are worked on to enhance the speed of the multiplier. Among this, algorithms based on Vedic mathematics are under focused as they can be used to design faster and low power multipliers. Vedic mathematics is based on sixteen sutras, out of them 'Urdhva Tiryakbhyam' and 'Nikhilam Navatashcaramam Dashatah' are noticed most. In this paper 32 bit implementation of 'Urdhva Tiryakbhyam' and 'Nikhilam Navatashcaramam Dashatah'. Multipliers in this paper are coded using Verilog language, it is synthesised and simulated using Xilinx ISE 14.5. In this paper, Urdhva Tiryakbhyam and Nikhilam sutra both algorithms are compared in terms of propagation delay and found that Urdhva Tiryakbhyam sutra performs faster for less bit input while Nikhilam sutra is faster for larger inputs. © 2016 IEEE.