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Design and Implementation of 16 bit RISC Processor on FPGA
Ms. Avanti Godbole, , Aditya Kolekar, Kunal Kasbekar
Published in IJCRT
Volume: 8.0
Issue: 6.0
Pages: 424.0 - 428.0
This project includes the designing of 16-Bit RISC processor and modeling of its components using Verilog HDL. The processor is based on Harvard architecture. The instruction set adopted here is extremely simple that gives an insight into the kind of hardware which should be able to execute the set of instructions properly. Along with sequential and combinational building blocks of a processor such as adders and registers more complex blocks such as ALU and memories have been designed and simulated. The modeling of ALU which has been done in this project is fully structural starting from half adders. At the end the semi-custom layout has been developed for ALU. Complex blocks such as memories have been modeled using behavioral approach, whereas simple blocks such as adders have been done through structural approach. The tools which have been used throughout the project work are ModelSim and Intel Quartus prime 18.1. For synthesis purpose the targeted FPGA device technology is ALTERA.
About the journal
JournalInternational Journal of Creative Research Thoughts
Open Access0