Sigma Delta ADC includes OP-AMP integrator, comparator and d flip-flop. Smoothing operation of OP-AMP integrator with sufficient gain and stability plays a significant role in Sigma Delta ADC for high frequency applications. Low power, Low cost comparator is demanded circuit in a market due to resolution of ADC converter depends on the comparator. Speed and variability of D flip-flop are required in sigma delta ADC to count the number of pulses after comparator. Hence this paper proposed modified zero cancelling method for stability and gain of OP-AMP integrator .This is achieved by modified biasing circuit of series feedback transistor. Resolution of ADC converter is prominently depend on comparator design. Modified comparator circuit appropriates for enhancing gain and for getting low power circuit due to proper biasing of transistor. The paper also aims to simulate Sigma delta ADC using single phase clocked feedback D flip-flop. Sigma Delta ADC is simulated in 180nm CMOS technology in Electric VLSI CAD Tool and TSMC BSIM3 is used as a model library. Supply voltage is 1.8v at 27◦ c temperature and Unity Gain Bandwidth (UGB) =5MHz.