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Design of FPGA Building Blocks Using LTspice®
Khairkar K., , Khambete Uday P., Jatana
Published in Institute of Electrical and Electronics Engineers Inc.
Pages: 256 - 259
This research work discusses the design and simulation of essential blocks of Field Programmable Gate Arrays (FPGA), such as N-channel metal-oxide-semiconductor (NMOS) Pass Transistor, Static Random-Access Memory (SRAM), Input/Output block (IOB), and Slice in LTspice. The blocks are referred from the Spartan-3 FPGA family and are designed in 180 nm technology. The blocks designed here can be configured to the desired functionality by placement and routing of the individual blocks in Verilog to routing (VTR). © 2021 IEEE.
About the journal
Journal2021 4th International Conference on Recent Developments in Control, Automation and Power Engineering, RDCAPE 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Open AccessNo