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Design of Low Power Full Adder Circuits Using CMOS Technique
Published in Institute of Electrical and Electronics Engineers Inc.
Pages: 293 - 296
1-bit different full adder circuits are designed using CMOS technique for low power consumption and less delay. These are implemented using Cadence Virtuoso at 180nm technology for 1.8V supply voltage. The parametric constraints such as power consumption, delay, area are compared with designed different full adder circuits and commented on which design gives best performance parameter. Power Delay Product defines the efficiency of the circuit. As low power design is the main research in VLSI, hence design the circuits which require low power, less area, less delay. The performance of complete design appertains to the performance of full adder circuit design. © 2019 IEEE.