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Hardware software co-design for CABAC entropy decoder
Published in Institute of Electrical and Electronics Engineers Inc.
Volume: 2016
Video compression is a key enabling technology for multimedia communication. The need for high-quality video processing in multimedia products is increasing, leading to enhancement in coding techniques. In future, multimedia systems require efficient video coding algorithms that provide high and efficient compression. The H.264 is one of the latest coding standards that provide high compression efficiency and network friendly representation compare to previous standards. In this paper, we present an architecture for Context-Based Adaptive Binary Arithmetic coding (CABAC) decoder which is used in H.264 as entropy decoding. CABAC gives higher compression efficiency by bringing higher implementation cost and complexity. In this work, we are focusing on designing an efficient and fast hardware and software co-design for CABAC which can be useful for the real-time application. A complex part of CABAC is design over FPGA hardware and remaining parts are on processing system (PS). For this work, we are using zynq-7000 based Zedboard which consists two parts one is Programing Logic (FPGA) and second is Processing system (Arm Cortex-9). We create an IP for a part of CABAC which can communicate with PS by AXI bus.