Clock gating is a prominent and an efficacious methodology adopted to decrease the dynamic power (clock power) utilization in complementary metal oxide semiconductor (CMOS) based circuits. The sole intent of gating a clock signal is to minimize its switching activity and thereby reduce significant amount of power utilization of the clock signal. Memories or storage elements are the integral part of the complex designs used in the modern day devices enabling storage of exhaustive and crucial values being processed. In this paper, we present the design and implementation of Random Access Memory (RAM) with reduced power consumption using clock gating technique on a Field Programmable Gate Array (FPGA). These memory elements can be either of synchronous or asynchronous nature. The memories discussed in the proposed work are synchronous in nature and hence reading and writing operations take place on the positive or rising edge of the clock. A gating logic is applied to lessen the superfluous transitions of the clock signal propagating along the clock network of the circuit. The target device (FPGA) for this work is Xilinx Spartan 6 and the design tool is Xilinx ISE 14.7 with the memories being modelled in Verilog HDL and simulation outputs shown in ISim. © 2019, Blue Eyes Intelligence Engineering and Sciences Publication. All rights reserved.