As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. This feature allows multiple functions to time-share the FPGA resources by exploiting reconfigurable area more efficiently. This paper designs a system using the high performance, high capacity Virtex-4 FPGA for hardware acceleration of JPEG Image Compression Algorithm along with Microblaze and Dynamic Partial Reconfigurable (DPR) using Xilinx's PlanAhead tool to achieve on-the-fly multiple Quality Factors (Q) of the compressed images corresponding to different Image Qualities and sizes in varying application scenarios.