To calculate the response physical circuit for the unknown condition, it is necessary to understand the physical circuit using mathematical model. The mathematical model is useful in case of design the control system or fault detection system for the external circuit. The proposed system deals with implementation of the mathematical model of the physical circuit using artificial neural network algorithms on FPGA. In the proposed system, the circuit under test (CUT) is connected to FPGA. FPGA applied test pattern input to the physical circuit, generate the weights and calculate the activation function. As the testing inputs are applied to the FPGA after successful training, the outcome results of the system are logically similar with a comparison of the external test circuit. To reduce the Register transfer level (RTL) logic design Vedic multiplier and divider using subtract and increment method is implemented in proposed system.