MIT-World Peace University (MIT-WPU) is a top educational institute located in Pune, India. It is recognized within&nbsp;UGC under Government of Maharashtra Act No. XXXV 2017.&nbsp;

It is part of the MIT group of institutions (established in 1983) which covers 10+ campuses across India and has more than 50,000+ students enrolled across various disciplines at a given point of time. The institute houses 15 schools ranging from Engineering &amp; Technology, Design, Pharmacy, Commerce, Governance among others. It offers undergraduate, postgraduate and PhD programs among different disciplines.&nbsp;

&nbsp;

MIT World Peace University

This paper proposes a new method of reducing the energy dissipation below that of quasi-adiabatic circuit. Adiabatic logic style is proving to be an attractive solution for low power digital design. Many researchers have introduced different adiabatic logic styles in last few years and proved that these are better than CMOS as far as power dissipation is concerned. In this paper, we present control circuits for sub-adiabatic energy dissipation and show that the energy dissipation of the quasi-adiabatic circuit can be further reduced if we control bulk-to-source voltage, VBS appropriately. All the inverter circuits are designed using 180nm technology in Cadence design environment. \textcopyright2009 IEEE.

School of Electronics & Communication Engineering

Engineering and Technology

World University root node

2009 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, ECTI-CON 2009

Achieving sub-adiabatic energy dissipation by varying VBS

Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances and switching frequencies. Energyrecovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. Such circuits achieve low energy dissipation by restricting current to flow across devices with very low voltage drop and by recycling the energy stored on their capacitors. This paper analyzes the performance of Pass Transistor Adiabatic Logic (PAL) against that of static CMOS. A standard 2X2 Barrel Shifter is used as the benchmark circuit for comparison due to its modular design. The analysis is carried out in cadence design environment using 180nm technology using cell based design approach. The simulation is done at various operating voltages, frequencies and load capacitances for each circuit family and technological node. \textcopyright2009 IEEE.

ICIIS 2009 - 4th International Conference on Industrial and Information Systems 2009, Conference Proceedings

Quasi-adiabatic 2X2 barrel shifter

Demands for low power electronics have motivated designers to explore new approaches to VLSI circuits. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances and switching frequencies. Energyrecovery circuitry, on the other hand, is a new promising approach to the design of VLSI circuits with very low energy dissipation. The supply voltage in adiabatic circuits in addition to providing the power to the circuit behaves as the clock of the circuit and for this reason is called power clock. One of the main concerns in the adiabatic logic circuits is the power clock generation. The design of a power clock generator is a challenging problem in this field. This paper discusses the design and simulation results of a VCO based power-clock supply generation for quasi-adiabatic circuits. The analysis is carried out in cadence design environment using 180nm technology using cell based design approach. \textcopyright2009 IEEE.

Implementation and analysis of VCO based power-clock supply generator

Adiabatic switching techniques based on energy recovery principle are one of the innovative solutions at circuit and logic level to achieve reduction in power. Many researchers had taken adder as a benchmark circuit but advantage of adiabatic can be taken only for a large digital circuit. Barrel Shifter is an important block in the processor design and not much effort has been done to minimize it's power dissipation. A barrel shifter needs nlog2n MUX for n-bit shifting and therefore designing a MUX for low power to use it as a repetitive block in the barrel shifter will considerably reduce the simulation time. This paper compares conventional CMOS based design with adiabatic All the circuits are designed using cell based design approach and 180nm device size in Cadence. The outcome of this research work will provide guidelines for designing barrel shifter using ultra low power MUX . \textcopyright 2008 IEEE.