MIT-World Peace University (MIT-WPU) is a top educational institute located in Pune, India. It is recognized within&nbsp;UGC under Government of Maharashtra Act No. XXXV 2017.&nbsp;

It is part of the MIT group of institutions (established in 1983) which covers 10+ campuses across India and has more than 50,000+ students enrolled across various disciplines at a given point of time. The institute houses 15 schools ranging from Engineering &amp; Technology, Design, Pharmacy, Commerce, Governance among others. It offers undergraduate, postgraduate and PhD programs among different disciplines.&nbsp;

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MIT World Peace University

Most of the real-time circuits are designed using the sequential logic, and designing sequential logic is slightly more complex than the combinational logic design. Alongside, memory devices play a very critical role in digital systems. A flip flop is a basic element in the designing of any sequential logic like the adders in the combinational logic design. In this paper, sequential logic circuits are designed using different technologies. This paper aims to design high-performance and highly efficient T flip flop and 4-bit asynchronous counter using the gate diffusion input (GDI), CMOS, and transmission gate-based (TGB) techniques and provides a comparison with each other for different parameters. In this paper, comparisons are shown for major VLSI aspects like area, power, delay, and power-delay product (PDP). Simulations are performed, and results are obtained for 180 nm technology with 1.8 V as input voltage using the Cadence virtuoso tool. © 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

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School of Electronics & Communication Engineering

Engineering and Technology

Lecture Notes in Electrical Engineering

Design and Comparison of Low-Power, High-Speed T Flip Flop, and 4-Bit Asynchronous Counter Using Various Design Techniques

Power efficiency of any design can be obtained in terms of PDP. The approach used to design any system defines the performance of system. Here, Gate Diffusion Input (GDI) design techniques as well as CMOS design techniques are used for designing full adder circuits. Full swing GDI technique is utilized to reduce power consumption and delay. Full swing GDI technique gives better speed of operation as compared to CMOS technique. While keeping these parameters at best GDI maintains low complexity of design. Full adder circuits are designed using 180 nm technology node in Cadence Virtuoso with supply voltage of 1.8 V. © 2021, Springer Nature Singapore Pte Ltd.

Implementation and Analysis of Low Power Consumption Full Swing GDI Full Adders

1-bit different full adder circuits are designed using CMOS technique for low power consumption and less delay. These are implemented using Cadence Virtuoso at 180nm technology for 1.8V supply voltage. The parametric constraints such as power consumption, delay, area are compared with designed different full adder circuits and commented on which design gives best performance parameter. Power Delay Product defines the efficiency of the circuit. As low power design is the main research in VLSI, hence design the circuits which require low power, less area, less delay. The performance of complete design appertains to the performance of full adder circuit design. © 2019 IEEE.

2019 3rd International Conference on Recent Developments in Control, Automation and Power Engineering, RDCAPE 2019

Design of Low Power Full Adder Circuits Using CMOS Technique

Wireless Sensor Networks (WSNs) is made up of a network of many compact and constrained sensors. Constrained Application Protocol (CoAP) was designed particularly for the constrained nodes and networks in WSNs as a unique web transfer protocol by the Internet engineering task force (IETF) developed. Time synchronization of these low power sensor modules is in high demand. This paper proposes a time synchronization module for CoAP and focuses on the energy efficiency of the WSN for CoAP using NS2, which will help to reduce the overall network overhead and minimize the energy consumption. © 2019 IEEE.

Proceedings - 2019 5th International Conference on Computing, Communication Control and Automation, ICCUBEA 2019

Time synchronization for CoAP using NS2

Audio playback devices like IPODs and MP3 players use Sigma Delta Digital to Analog Converters (DACs) where the size and power consumption is of prime importance. Digital modulator is the most important part of Sigma Delta DACs. This paper presents a new approach for the implementation of a sample digital MASH 1-1 and MOD 2 modulator using Gate Diffusion Input (GDI) technique. The same modulators are also implemented in standard CMOS technology and are compared for the tone frequencies of the audio frequency range. The proposed modulators using GDI method provide a significant improvement in the area, power, and power delay product as compared to CMOS. The gate level simulation using WinSpice with 0.18 µm technology confirms the usefulness of the presented structures.

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Journal of King Saud University – Engineering Sciences

Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

Direct Charge Transfer Switched Capacitor (DCT-SC) DAC is the internal DAC used in Delta-Sigma (ΔΣ) DAC which works on Over-Sampling concept. The Switched Capacitor DAC mainly suffers from mismatch among capacitors. Mismatch among capacitors in DAC, causes nonlinearity between output and input. Dynamic Element Matching (DEM) technique is used to match the capacitors. According to element selection logic there are many types. In this paper Data Weighted Averaging (DWA) technique is used for mismatch shaping. In this paper the 4 bit DCT-SC-DAC with DWA-DEM technique is implemented using WINSPICE simulation software in 180nm CMOS technology. DNL for DAC with DWA is ±0.03 LSB and INL is ± 0.02LSB. © 2015 IEEE.