MIT-World Peace University (MIT-WPU) is a top educational institute located in Pune, India. It is recognized within&nbsp;UGC under Government of Maharashtra Act No. XXXV 2017.&nbsp;

It is part of the MIT group of institutions (established in 1983) which covers 10+ campuses across India and has more than 50,000+ students enrolled across various disciplines at a given point of time. The institute houses 15 schools ranging from Engineering &amp; Technology, Design, Pharmacy, Commerce, Governance among others. It offers undergraduate, postgraduate and PhD programs among different disciplines.&nbsp;

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MIT World Peace University

Cryptanalysis is used to analyze the strength of a cryptographic algorithm. Various cryptanalytic attacks against AES algorithm target reduced-round variants. These attacks are theoretical and are generally considered infeasible due to the demand for a large number of computations. To meet this high-computational requirement, an FPGA-based High-Performance Computing (HPC) platform is presented in this paper. FPGAs are advantageous for implementing cryptanalytic attacks, as the modular arithmetic is implemented more efficiently in FPGAs as compared to GPUs. The proposed HPC platform consists of four Spartan6 FPGAs connected in a mesh topology. A brute force cryptanalytic attack on the AES algorithm with a 128-bit key is implemented on the proposed HPC platform. Four-AES key search engines are designed in each FPGA. Thus, 16-AES key search engines are instantiated in parallel to perform AES cryptanalysis using different keys in parallel. To allocate distinct the key space to the 16 AES key search engines, an efficient key generator is also proposed in this work. The proposed architecture achieves a computational complexity of 2124 for an attack against 10-rounds AES algorithm. © 2020, Springer Nature Singapore Pte Ltd.

School of Electronics & Communication Engineering

Engineering and Technology

World University root node

Computing in Engineering and Technology. Advances in Intelligent Systems and Computing

FPGA-Based High-Performance Computing Platform for Cryptanalysis of AES Algorithm

The automotive sector is constantly and rapidly upgrading and deploying advanced features intocontemporary vehicles. To integrate these advanced features, numerous electronic systems are needed. Several controlmodules are used for enabling these systems to act jointly. Engine Control Module is a crucial part of vehicle’s EngineManagement System (EMS). Expanding interest for progressively controlled security features, traveler comfort, andoperational ease in vehicles requires an exhaustive utilization of electronic control units (ECU). The Engine ControlModule (ECM) provides the brains for the engine of the vehicle. It controls the fuel mixture; timing and emissionscontrol system and variety of other systems and sensors. This paper presents a review on ECU, different types ofcontrol units in vehicle, automotive communication protocols and working of an ECU.

International Journal for Research in Engineering Application & Management (IJREAM)

Engine Control Module: A Review

Fuel injection system is an indispensible part of thepresent day automobiles. The depletion of the fuels along withcontinuous surge in the fuel prices has made it imperative to usefuel economically and restricting the wastage to a minimum.Contrary to the carburetor, using predefined amount of fuelirrespective of the environment, Fuel Injection System uses justthe required amount of fuel based on the operating conditions assensed by the Engine Control Module (ECM). Numerousparameters are required to be sensed by the ECM to achieveoptimum efficiency of the engine. To handle the processing ofsuch large number of parameters, a robust architecture isrequired. This paper presents the design and implementation ofECM utilized in Electronic Fuel Injection (EFI) system on a FieldProgrammable Gate Array. The ECM architecture discussed inthe proposed system is computationally efficient enough to fulfillever-increasing functionalities of the ECM. The main objective ofthis research is to sense the parameters required for the ECManalysis and to interpret and analyze this data and accordinglycontrol the solenoid (actuator). The CAN controller is alsodeployed in an FPGA to facilitate the communication betweenECM and Human Machine Interface (HMI) to indicate theparameters sensed by the sensor on the LCD. The target device(FPGA) for this work is Xilinx Spartan 3E and the design tool isXilinx ISE 14.7 with the ECM and CAN controller being modeledin Verilog Hardware Description Language (HDL).

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International Journal of Innovative Technology and Exploring Engineering (IJITEE)

FPGA Based Engine Control Module for Fuel Injection System

Data transferred in an electronic way is vulnerable to attacks. With an aim to protect data for secure communication, a new Hybrid non pipelined Advanced Encryption Standard (AES) algorithm based on traditional AES algorithm with enhanced security features is proposed in this work. Abysmal analysis of the AES algorithm implies that the security of AES lies in the S-box operations. This paper presents a new approach for generating S-box values (modified S-box) and initial key required for encryption/encryption (improved key generation) using PN Sequence Generator. The AES algorithm with proposed modifications shows significant improvement in the encryption quality as compared to traditional AES algorithm. The traditional AES algorithm equipped with proposed novel modified S-box technique and improved key generation technique gives an avalanche effect of 60% making it invulnerable to attacks. The proposed design is synthesized on various Field Programmable Gate Array (FPGA) devices and compared to the existing designs resulting in significant improvement in throughput. The proposed design is implemented on Spartan6 FPGA device.

Journal of King Saud University – Engineering Sciences (2018)

An efficient AES implementation using FPGA with enhanced security features

Information Security is a major issue worldwide. Various steps are being taken to improve and upgrade security measures. Border crossings across countries have become one of them. Therefore the use of traditional passports has lead to an improvement in the name of E-passports. E-passports are a more secured and are denoted by a symbol. E-passports contain a small chip which stores the data of passport holder. To protect this data Cryptography is widely used. This paper shows the comparison of modular multiplication methods used for RSA algorithm for 1024 bit key length. Xilinx ISE 14.3 platform is used to perform this encryption and decryption process targeting Virtex-5 FPGA board.

2016 International Conference on Inventive Computation Technologies (ICICT)

Implementation of cryptography algorithm for E-passport security

In a country like India, patients are monitored in their recovery period, so the cost of hospitalization is also increasing day by day. The physiological parameters like body temperature, heart beat rate are monitored during recovery period of patients. This is done using a 'Smart Non-Invasive Wireless Physiological Monitoring System', where patients are monitored remotely. Impact sensors are used, which detects the fall of patients, so that immediate help is provided to them. In this paper the temperature, heart beat rate and impact sensors are used to measure physiological parameters which are then analysed and transmitted to PC through ZIGBEE wirelessly. Using GUI, parameters are monitored on PC by medical professionals. The high fluctuations in the parameters will be reported to doctors as a critical condition through GSM. © 2014 IEEE.

2014 International Conference on Embedded Systems (ICES)

Smart non-invasive wireless physiological monitoring system

With the advent of low cost Field Programmable Gate Arrays (FPGA's), building special purpose hardware for computationally intensive applications has now become possible. Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. This paper presents the design for Hardware implementation of Data Encryption Standard (DES) cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Iterative and Loop unrolled DES architecture are implemented. The aim of this work is to make cryptanalysis faster and better. © 2012 IEEE.